Vacuum Chip Scale Package

Fraunhofer IMS has developed a chip-scale package (CSP) for customer-specific microsystems, such as MEMS resonators or acceleration sensors. It offers significant advantages over classical packages made of metal, plastic or ceramics, as it is hardly larger than the chip itself. Furthermore, it allows sensors to be operated in vacuum or inert gas and it is also cost-effective and can be manufactured in large quantities.

The Fraunhofer IMS has realized the smallest possible vacuum package for uncooled IR imagers by developing a vacuum chip-scale package with an integrated infrared transparent window. Microbolometers as sensing elements of an uncooled infrared sensor function according to the thermal principle and therefore have to operate in a vacuum package to reduce thermal losses due to gas convection. This vacuum chip-scale package contains an IR transparent window with an anti-reflection layer, and in addition to the size advantage, it also has significant cost advantages due to the integrated manufacturing process. The vacuum chip-scale package technology can also be universally used for vacuum or protective casing in applications outside of uncooled infrared sensors.

This vacuum chip-scale package contains an IR-transparent window with an anti-reflection layer and, in addition to the size advantage, also has significant cost advantages due to the integrated manufacturing process.

The vacuum chip scale package consists of the CMOS substrate in the lower part, which contains the readout circuit (ROIC) and the microbolometer array. An electrochemically deposited solder frame surrounds the microbolometer array. By means of a flip-chip process, an IR-transparent cover with a broadband anti-reflection layer on both sides is placed on the solder frame.

Finally, a vacuum soldering process takes place in the wafer assembly, where the solder frame is hermetically sealed with the IR transparent lid, thus realizing a micro-cavity with a very good vacuum level around the microbolometer array. To ensure the vacuum level and long-term stability, a getter located on the inside of the lid is activated during the soldering process.

In the vacuum chip-scale package developed by Fraunhofer IMS, the IR-transparent lids are placed only on readout circuits tested as "good". Furthermore, the size of the IR transparent lids can be optimized independently of the size of the readout circuit, so that there are significantly more IR transparent lids on a lid wafer than there are readout circuits on a substrate wafer.

The sawing process for separating the readout circuits of the substrate wafer is also significantly simplified, since it is not necessary to expose the pad rim for electrical connection of the readout circuits in several sawing steps. This form of optimized wafer level process results in significant cost advantages for the realized vacuum package in direct comparison to the classic wafer level package, where a separate complete lid wafer must be used for each substrate wafer.

The entire production of the chip-scale packages takes place in the Microsystems Technology Lab&Fab of the Fraunhofer IMS on 200 mm wafers. Wafers produced at Fraunhofer IMS as well as wafers provided by customers can be used for this purpose.

The lids used for encapsulation can also be adapted to the target application and manufactured at the Fraunhofer IMS. By choosing a suitable lid size, the bond pads of the microsystem chips can be freely accessible after the production of the chip-scale package, so that a functional test is still possible at wafer level and chips can be selected for further processing after separation.