High Temperature Electronic

Press Release /

High temperature IC design and fabrication

Fraunhofer IMS has more than a decade of expertise in the design and wafer processing of high temperature integrated circuits and systems for operating temperatures up to 250°C.

Based on numerous existing analog and digital IP blocks we realize application specific integrated circuits usually including full custom design blocks. Our designs range from highly specialized sensor read-out electronics to System on Chip solutions including analog components for signal conditioning, analog / digital converters and even embedded microcontrollers.

Fraunhofer IMS operates a complete CMOS wafer line offering various CMOS processes with a feature size down to 0.35μm. The dedicated high temperature capable Silicon-On-Insulator (SOI) CMOS processes expand the operating range of CMOS for use in harsh environments. They allow the realization of mixed signal integrated circuits for operating temperatures up to 250°C. Various backend and assembly options are available, e.g. gold plating for reliable high temperature pad metallization. Fraunhofer IMS provides all services from first conceptual analysis to design, pilot production and test of high temperature integrated circuits.

High Temperature Electronics Service and Know-How

Service and Support

  • Feasibility studies
  • System specification and concept development
  • Mixed signal IC design
  • Sensor integration
  • CMOS processing, assembly and test
  • Reliability tests
  • Application support

High Temperature Know-How

  • ASICs for harsh environment with operating temperature up to 250 °C
  • High Temperature SOI CMOS technology
  • High Temperature mixed signal design
    - Analog and digital IP blocks
    - Embedded microcontroller
    - System on Chip (SoC)
  • Backend metallization (gold plating)
  • Packaging solutions

High Temperature SOI CMOS technology

Fraunhofer IMS operates a 200 mm CMOS wafer line. Our proprietary H10 and H035 High Temperature Silicon On Insulator (SOI) CMOS processes provide the following features:

  • Feature size 1μm / 0.35 μm
  • Dual gate oxide (H035)
  • Thick gate oxide for analog devices (up to 30V)
  • Thin gate oxide for digital transistors (H035)
  • Analog grade CMOS devices (VDD 5V)
  • Passive devices R, C, PIN Diodes
  • 3.3 V digital devices
  • Non volatile memories
  • Integrated sensors
  • Up to four layers of high temperature Tungsten metallization
  • Backend options: e.g. gold pad metallization
  • Multi-project wafer (MPW) services

Fraunhofer IMS provides a process design kit for Cadence including IO cells, digital cells and device library. Analog blocks are available on request. All devices are characterized for an extended temperature range up to 250°C.