3D-Integration in Microelectronics

In recent decades, research and development in the field of micro- and nano-electronics have led to ever smaller structure sizes and continuously increasing integration densities of sensors, memories and processing circuits. However, due to the achievement of physical limitations, the enormous technological growth stagnates on a wafer level. The 3D integration of micro/nanoelectric devices enables a vertical arrangement of different system components and offers a way to continue the trend of compact and high performance devices ("More than Moore"). 3D integration opens up further advantages along with the densely packed design:

  • Cost reduction
  • Shorter connection paths
  • Higher integration density
3D wafer-to-wafer bond from sensor and circuit wafer before post-processing
© Fraunhofer IMS
3D wafer-to-wafer bond from sensor and circuit wafer before post-processing
µVia structures for front-side silicon through-hole plating in wafer-to-wafer bonding process.
© Fraunhofer IMS
µVia structures for front-side silicon through-hole plating in wafer-to-wafer bonding process.
Cu/Sn microbumps for contacting by SLID method
© Fraunhofer IMS
Cu/Sn microbumps for contacting by SLID method

By exploiting the third dimension and the possibility of heterogeneous integration, structures from different process lines can be combined. For example, 3D integration allows optical sensors to be bonded directly to the associated interpreting and signal processing circuit logic. As current new developments place ever higher demands on the detectors, it is increasingly necessary to manufacture the detectors in specialized technologies and to produce the signal-processing circuit parts in a technology with very small structures. This allows, for example, the interpretive readout circuit to be outsourced to the third dimension and the optically active area to be enlarged, thus significantly increasing sensitivity.

Fraunhofer IMS supports different technologies for 3D integration on 200 mm wafers.


Fraunhofer IMS has a direct oxide-to-oxide bonding process for 3D integration, which is performed at CMOS-compatible temperatures below 400 °C. Direct wafer bonding is based on the formation of covalent siloxane (Si-O-Si) bonds. For this purpose, the wafer surfaces are activated in oxygen plasma to generate silanol (Si-OH) groups under an H2O atmosphere. The wafers are aligned and contacted to each other so that hydrogen bonds are formed in the bond interface region. Finally, the pair of wafers is heated to over 250 °C and strong covalent siloxane bonds are formed by the diffusion of water away. To produce a high-quality bond, the following surface properties must be taken into account:

Topology, Microroughness, Bending, Particle contamination



Based on many years of experience at Fraunhofer IMS in CMOS and MEMS processes as well as in packaging technology, optimized stress compensation and chemical mechanical planarization (CMP) processes as well as adapted layout designs for W2W bonding could be developed. With the process optimizations, a shear strength of more than 4 kg/mm2 and a precision accuracy of the wafer bond of less than 2 µm are achieved.

The front-side silicon through-silicon vias (TSV) are filled with an ALD (Atomic Layer Deposition) optimized material stack. Different µVia variants allow the process to be adapted to individual customer design specifications.

Solid-liquid interdiffusion (SLID)

Chip-to-wafer bonding at Fraunhofer IMS is based on the solid-liquid interdiffusion (SLID) process, which uses the production of an intermetallic phase in a two-metal system to create high-temperature resistant contacts at low process temperature. For this purpose, a low-melting metal is brought into contact with a suitable metal partner with a higher melting temperature and melted. Diffusion processes occur at the interfaces and an intermetallic phase is formed. Depending on the material combination used, contacts can be produced that withstand temperatures of 400 °C to 600 °C.

Flip-chip process

For 3D integration, the Fraunhofer IMS uses the flip-chip process. For assembly, the chip is soldered onto the wafer with the active surface facing down. The chip size to be processed can be a few mm or even in the µm range. Contacting is established via microbumps, which are aligned with each other with high precision (precision accuracy < 5 µm). The bump size ranges from a few µm to 100 µm. For the fabrication of the microbumps, Fraunhofer IMS offers electrodeposition of the following materials:

  • Copper (Cu)
  • Tin (Sn)
  • Gold (Au)
  • Nickel (Ni)

Based on many years of process experience, the CuSn and Ni/Au/Sn SLID bonding process has been established at Fraunhofer IMS. The CuSn and Ni/Au/Sn bump contacts produced are stable at temperatures up to 675 °C and 522 °C, respectively, and withstand more than 1000 temperature cycles (-55 °C to 150 °C).

With wafer-to-wafer and chip-to-wafer bonding, two powerful and established processes for 3D integration are available at Fraunhofer IMS.

Our technologies - Innovations for your products

Atomic Layer Deposition (ALD)

Atomic Layer Deposition (ALD) is a process for the deposition of extremely thin and homogeneous layers. It enables NEMS devices for e.g. gas and biosensors.


Technology process for the production of customized uncooled infrared sensors for applications in the wavelength range 3 µm to 5 µm or 8 µm to 14 µm.

Vacuum Chip-Scale-Package

We have implemented the smallest possible vacuum package for uncooled IR imagers using vacuum chip scale packages (CSP) technology.

Pressure Sensors

We operate processes for the manufacture of pressure sensor systems in both CMOS and MST production lines.

SPAD in focus

Highly sensitive image sensors with adapted microlens arrays 

Our technology areas - Our technologies for your development

Image Sensors

Development of individual sub-steps up to the complete customer-specific process.

Biofunctional Sensors

Tools for medical diagnostics.

Specialized technologies

The Fraunhofer IMS also offers special technologies e.g. high-temperature technology.


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