License-free RISC-V core for FPGA and ASIC
With the AIRISC core, the Fraunhofer IMS places its powerful RISC-V embedded processor core for sensor tasks under an open source license, which also allows the use for commercial products.
With the powerful 32-bit AIRISC core, products with FPGAs can be developed quickly and cost-effectively. The conversion into a (mixed-signal) ASIC is subsequently possible in record time due to the identical code base and does not require a commercial license for the basic core. The AIRISC core is fully implemented in Verilog, allowing synthesis with any common tool.
The AIRISC open source package includes, in addition to the Verilog description for the core, the necessary support for easy software development (Board Support Package) and a basic example application. The IMS also maintains a catalog of paid add-on features for accelerating sensing tasks,
in particular for the areas:
- cognitive power electronics and control
- medical wearables and time series analysis
- image processing and LIDAR
- AI model inference and training using AIfES.
A safety-certified variant of the core, flows for various ASIC fabrication technologies, and training and support services are available through the IMS.
The code for the AIRISC Core Complex is on Github.